Published on Apr 02, 2024
The principal of Built-in-test and self-test has been widely applied to the design and testing of complex, mixed-signal electronic systems, such as integrated circuits (IC s) and multifractional instrumentation [1].
A system with BIT is characterized by its ability to identify its operation condition by itself, through the testing and diagnosis capabilities built into its in structure. To ensure reliable performance, testability needs to be incorporated into the early stage of system and product design. Various techniques have been developed over the past decades to implement the BIT technique.
In the semiconductor, the objective of applying BIT is to improve the yield of chip fabrication, enable robust and efficient chip testing and better scope with the increasing circuit complexity and integration density. This has been achieved by having an IC chip generate its own test stimuli and measure the corresponding responses from the various elements within the chip to determine its condition.
In recent years, BIT has seen increasing applications in other branches of industry, eg. manufacturing, aerospace and transportation and for the purposes of system condition monitoring. In manufacturing systems, BIT facilitates automatic detection of toolwear and breakage and assists in corrective actions to ensure part quality and reduce machine downtime.
BIT techniques are classified:
a. on-line BIT
b. off-line BIT
On-line BIT:
It includes concurrent and nonconcurrent techniques. Testing occurs during normal functional operation.
Concurrent on-line BIST - Testing occurs simultaneously with normal operation mode, usually coding techniques or duplication and comparison are used. [3]
Nonconcurrent on-line BIST - testing is carried out while a system is in an idle state, often by executing diagnostic software or firmware routines
System is not in its normal working mode it usually uses onchip test generators and output response analysers or micro diagnostic routines. Functional off-line BIT is based on a functional description of the Component Under Test (CUT) and uses functional high-level fault models. Structural off-line BIT is based on the structure of the CUT and uses structural fault models.
IC s entering the market today is more complex in design with a higher integration density. This leads to increased vulnerability of the chip to problems such as cross talk noise contamination, and internal power dissipation. These problems reduce the reliability of the chip. Further more, with increased chip density, it becomes mo0re difficult to access test points on a chip for external testing.
Also, testing procedures currently in use are time consuming, presenting a bottleneck for higher productivity [2]. These factors have led to the emergence of BIT in the semiconductor industry as a cost effective, reliable, and efficient quality control technique. Generally, adding testing circuitry on to the same IC chip increases the chip area requirement conflicting with the need for system miniaturization and power conception reduction.
On the other hand, techniques have been developed to allow the circuit-under-test (CUT) to be tested using existing on-chip hardware, thus keeping the area overhead to a minimum [1]. Also, the built-in-test functions obviate the need for expensive external testers. Further more; since the chip testing procedure is generated and performed on the chip itself, it takes less time as compared to one external testing procedure.
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