Published on Nov 30, 2023
Synchronous DRAM (SDRAM) has become a mainstream memory of choice in design due to its speed, burst access and pipeline features. For high-end applications using processors, the interface to the SDRAM is supported by the processor’s built-in peripheral module.
However, for other applications, the system designer must design a controller to provide proper commands for DRAM initialization, read/write accesses and memory refresh.
This SDRAM controller reference design, located between the SDRAM and the bus master, reduces the user’s effort to deal with the SDRAM command interface by
providing a simple generic system interface to the bus master • Simplifies SDRAM command interface to standard system read/write interface.
• Internal state machine built for SDRAM power-on initialization.
• Read/write cycle access time optimized automatically according to the SDRAM timing spec and the mode it’s configured to.
• Dedicated auto-refresh request input and acknowledge output for SDRAM refresh.
• Easily configurable to support different CAS latency and burst length
VHDL
Simulation: ModelSim
Synthesis: XiLinx
