Published on Nov 30, 2023
This paper presents an efficient architecture to implement low power variable block size motion estimation (VBSME) using full search.
Power reduction is achieved by performing the search in two steps: low pixel resolution and full pixel resolution. We analyzed the computation and memory units needed to support these two search modes.
The proposed architecture reduces the total energy consumption by 50% with 6% additional area compared to the conventional architecture.
Motion estimation (ME) has been identified as the main source of power consumption in video encoders. It consumes more than 40% of the total power used in video compression. This results from the high computational load needed to predict the current frame.
Full-search motion estimation predicts the current macro block by finding the candidate that gives the minimum sum of absolute difference (SAD)
In proposed system we analyze the hardware implementation for this technique in terms of area, power and energy efficiency. The aim of this architecture is to include low power capability on top of the existing full search motion estimation
VHDL
Simulation: modelsim5.8c
Synthesis: Xilinx 9.1
