Published on Apr 02, 2024
Electronics without silicon is unbelievable, but it will come true with the evolution of Diamond or Carbon chip. Now a day we are using silicon for the manufacturing of Electronic Chip's. It has many disadvantages when it is used in power electronic applications, such as bulk in size, slow operating speed etc. Carbon, Silicon and Germanium are belonging to the same group in the periodic table.
They have four valance electrons in their outer shell. Pure Silicon and Germanium are semiconductors in normal temperature. So in the earlier days they are used widely for the manufacturing of electronic components. But later it is found that Germanium has many disadvantages compared to silicon, such as large reverse current, less stability towards temperature etc so in the industry focused in developing electronic components using silicon wafers
Now research people found that Carbon is more advantages than Silicon. By using carbon as the manufacturing material, we can achieve smaller, faster and stronger chips. They are succeeded in making smaller prototypes of Carbon chip. They invented a major component using carbon that is "CARBON NANOTUBE", which is widely used in most modern microprocessors and it will be a major component in the Diamond chip
In single definition, Diamond Chip is an electronic chip manufactured on a Diamond structural Carbon wafer. OR it can be also defined as the electronic component manufactured using carbon as the wafer. The major component using carbon is (cnt) Carbon Nanotube. Carbon Nanotube is a nano dimensional made by using carbon. It has many unique properties.
Pure Diamond structural carbon is non-conducting in nature. In order to make it conducting we have to perform doping process. We are using Boron as the p-type doping Agent and the Nitrogen as the n-type doping agent. The doping process is similar to that in the case of Silicon chip manufacturing. But this process will take more time compared with that of silicon because it is very difficult to diffuse through strongly bonded diamond structure. CNT (Carbon Nanotube) is already a semi conductor.
As the size of the carbon atom is small compared with that of silicon atom, it is possible to etch very smaller lines through diamond structural carbon. We can realize a transistor whose size is one in hundredth of silicon transistor.
Diamond is very strongly bonded material. It can withstand higher temperatures compared with that of silicon. At very high temperature, crystal structure of the silicon will collapse. But diamond chip can function well in these elevated temperatures. Diamond is very good conductor of heat. So if there is any heat dissipation inside the chip, heat will very quickly transferred to the heat sink or other cooling mechanics.
Carbon chip works faster than silicon chip. Mobility of the electrons inside the doped diamond structural carbon is higher than that of in he silicon structure. As the size of the silicon is higher than that of carbon, the chance of collision of electrons with larger silicon atoms increases. But the carbon atom size is small, so the chance of collision decreases. So the mobility of the charge carriers is higher in doped diamond structural carbon compared with that of silicon.
For power electronics application silicon is used, but it has many disadvantages such as bulk in size, slow operating speed, less efficiency, lower band gap etc at very high voltages silicon structure will collapse. Diamond has a strongly bonded crystal structure. So carbon chip can work under high power environment. It is assumed that a carbon transistor will deliver one watt of power at rate of 100 GHZ. Now days in all power electronic circuits, we are using certain circuits like relays, or MOSFET inter connection circuits (inverter circuits) for the purpose of interconnecting a low power control circuit with a high power circuit .If we are using carbon chip this inter phase is not needed. We can connect high power circuit direct to the diamond chip
This method includes simple vapourization of sic. Sic is vapourized at very high temperature, in the presence of the vacuums at elevated temperatures silicon will vapourize escape from the crystal structure. Carbon atoms will bond it self-together to form carbon nanotube. This method is considered as the most pure method of manufacturing carbon nanotube, because in this method no catalysts are used so the result is no impurity carbon nanotube. So it is used for the manufacturing of carbon nanotubes for the laboratory purposes.
Constructive destruction is new technique invented by IBM. It not a manufacturing method of carbon nanotube; but it is manipulated method. By the three methods mentioned above, we are getting both singled walled carbon nanotube and multi walled carbon nanotubes. All electronic applications require semi conducting carbon nanotubes. This method to separate semi conducting carbon nanotubes from metallic carbon nanotubes. It follows below step –
1. Deposit stick together carbon nanotubes on silicon dioxide water.
2. Use photographic methods to make electrodes on both ends of the carbon nanotube.
3. Make a gate electrode on the silicon dioxide water.
4. Using silicon dioxide water it self as the electrode, the scientist’s switched off. The semi conducting nanotubes by applying appropriate voltage to the silicon dioxide water. Which blocks any current flow through the semi conducting nanotube.
5. The metallic carbon nanotubes are unprotected, and appropriate carbon voltage is applied to destroy the metallic carbon nanotubes.
6. Result:- a dense array of un harmed semi conducting carbon nanotubes are formed, which can be used for transistor manufacturing.
Atomic force microscopy (AFM) is a method of measuring surface topography on a scale from angstroms to 100 microns. The technique involves imaging a sample through the use of probe or tip, with a radius of 20nm. The tip is held several nanometers above the surface using a feedback mechanism that measures surface-tip interaction on the scale of nano Newton’s. Variation in tip height are recorded while the tip is scanned repeatedly
Across the sample, producing a topographic image of the surface.
In addition to basic AFM, the instrument in the Microscopy Suite is capable of producing images in a number of other modes, including tapping, magnetic force, and pulsed force. In tapping mode, the tip is oscillated above the sample surface, and data may be collected from interactions with surface topography, stiffness, and adhesion. This result in an expanded number of image contrast methods compared to basic AFM. Magnetic force mode imaging utilizing a magnetic tip to enable the visualization of magnetic domains on the sample. In electrical force mode imaging a charged tip is used to locate and record variations in surface charge. In pulsed force mode (Witec), the sample is oscillated beneath the tip, and a serious of pseudo force – distance curves are generated. This permits the separation of sample topography, stiffness, and adhesion values, producing three independent images. Or three individual sets of data , Simultaneously.
Carbon nanotube are used for inter connections inside the chip. Metallic and semi conducting nanotubes are highly conducting; they can pass a current of one million amperes per cm square without any deturiation. Switching time carbons annotate is very small compared with that of ordinary copper conductors. So it is found that carbon nanotubes can be successfully used for the interconnections between two components in the electronic chip. Metallic or semi conducting carbon nanotubes is used for this purpose. There is no need to create deep, narrow trenches on the silicon wafer in which to burry copper conductors.
At first we are placing catalyst that is to grow microscopic, whisker-like carbon nanotubes on the surface of the silicon wafer. The catalysts are very carefully placed, so that the direction of carbon nanotube growth can be clearly defined. After that we are doing a chemical vapour deposition on the surface of the wafer. The gas used here is methane. It will trigger the growth of carbon nanotube in the wafer. After the growth of the carbon nanotube we are depositing a layer of silicon over the carbon nanotube grown on the chip to fill the spaces between the carbon nanotube. Finally the surface is finished flat.
MOORE’S LAW states that the number of transistors possible in a fixed area is doubling in every 18 months. It is predicted that in the year 2011, there will be condition that we have to print a line whose width is smaller than the spacing between two silicon atoms. This is not possible with silicon wafers. This is the main reason for developing carbon chips. The size of the carbon is less than that of silicon, so we can print such a small line through the Diamond structural Carbon. So that we can make smaller dimensional chips.
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