Published on Nov 30, 2023
This paper presents a deterministic BIST technique that can efficiently achieve complete fault coverage without using any storage devices.
A novel test structure containing a self-feedback logic unit and a circular shift register is proposed by which all the required deterministic patterns can be generated on-chip in real time.
Experiments on ISCAS 85 benchmark circuits show that compared with previous work addressing the same problem our technique requires much less test time to achieve 100% fault coverage for all testable stuck-at faults
VHDL
Simulation: ModelSim XE III 6.4b.
Synthesis: XiLinx ISE 10.1.
