Published on Nov 30, 2023
This project details with major design considerations before the design and implementation of a 15-tap programmable Finite Impulse Response (FIR) Filter. Firstly, two adder structures are examined and compared in terms of area, speed and power consumption.
In this delay-balancing techniques were applied to the block to reduce power consumption further The mathematical structure of a 3-tap FIR filter is shown below. The signal input is a number representing the magnitude of a sampled analogue signal.
The z-1 blocks store their input and delay it by one sample period.
The Cox blocks contain the coefficients that shape the FIR filter frequency response. The design specification for the system to be designed details the coefficients for the test of the system as signed floating-point numbers
VHDL
Simulation: ModelSim XE III 6.4b.
Synthesis: XiLinx ISE 10.1.
